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ds1672 i 2 c 32-bit binar y counter rtc www.maxim-ic.com general description the ds1672 incorporates a 32-bit counter and power-monitoring functions . the 32-bit counter is designed to count seconds and can be used to derive time-of-day, w eek, month, month, and year by using a software algorithm. a precision, temperature-compensated reference and comparator circuit monitors the status of v cc . when an out-of-toleran ce condition occurs, an internal power-fail signal is generated that forces the reset to the active state. when v cc returns to an in-tolerance condition, the reset signal is kept in the active state for a period of time to allow the power supply and pr ocessor to stabilize. 1 of 15 rev: 031406 features ? 32-bit counter ? i 2 c * serial interface ? automatic power-fail detect and switch circuitry ? power-fail reset output ? low-voltage oscill ator operation (1.3v min) ? trickle-charge capability ? underwriters laboratory (ul) recognized ? -40 ?c to +85 ? c operating temperature range typical operating circuit pin configuration top view 1 v cc x1 8 2 7 ds1672 x2 r st v backup scl 3 6 gnd sda 4 5 dip so ? sop *p s, i a li e c s t s.
ds1672 2 of 15 ordering information part temp range voltage (v) pin-package top mark* ds1672-2 -40c to +85c 2.0 8 dip (300 mils) ds1672-2 ds1672-3 -40c to +85c 3.0 8 dip (300 mils) ds1672-3 ds1672-33 -40c to +85c 3.3 8 dip (300 mils) ds1672-33 ds1672s-2 -40c to +85c 2.0 8 so (150 mils) ds1672-2 ds1672s-2+ -40c to +85c 2.0 8 so (150 mils) d1672-2 ds1672s-3 -40c to +85c 3.0 8 so (150 mils) ds1672-3 ds1672s-3+ -40c to +85c 3.0 8 so (150 mils) d1672-3 ds1672s-33 -40c to +85c 3.3 8 so (150 mils) ds167233 ds1672s-33+ -40c to +85c 3.3 8 so (150 mils) d167233 ds1672s-3/t&r -40c to +85c 3.0 8 so (150 mils)/tape and reel ds1672-3 ds1672s-3+t&r -40c to +85c 3.0 8 so (150 mils)/tape and reel d1672-3 ds1672s-33/t&r -40c to +85c 3.3 8 so (150 mils)/tape and reel ds167233 ds1672s-33+t&r -40c to +85c 3.3 8 so (150 mils)/tape and reel d167233 ds1672u-2 -40c to +85c 2.0 8 ? sop (3mm) 1672 rr -2 ds1672u-2+ -40c to +85c 2.0 8 ? sop (3mm) 1672 rr -2 ds1672u-3 -40c to +85c 3.0 8 ? sop (3mm) 1672 rr -3 ds1672u-3+ -40c to +85c 3.0 8 ? sop (3mm) 1672 rr -3 ds1672u-33 -40c to +85c 3.3 8 ? sop (3mm) 1672 rr -33 ds1672u-33+ -40c to +85c 3.3 8 ? sop (3mm) 1672 rr -33 ds1672u-33/t&r -40c to +85c 3.3 8 ? sop (3mm)/tape and reel 1672 rr -33 ds1672u-33+t&r -40c to +85c 3.3 8 ? sop (3mm)/tape and reel 1672 rr -33 + denotes a lead(pb)-free/rohs-compliant device. * a + anywhere on the top mark denotes a lead-fr ee device. rr = 2-digit alphanumeric revision code.
ds1672 3 of 15 absolute maxi mum ratings voltage range on any pin relative to ground?????????????????..-0.5v to +6.0v operating temperature ra nge (noncondensing) ...????????????????-40 ?c to +85 ?c storage temperature range????????????????????????.-55 ?c to +125 ?c soldering temperature????????????????.see ip c/jedec j-std-020 specification this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not imp lied. exposure to absolute maximum rating c onditions for extended periods of time can affect device reliability. recommended dc oper ating conditions (t a = -40 ?c to +85 ?c) parameter symbol min typ max units notes ds1672-2 v cc 1.8 2.0 2.2 ds1672-3 v cc 2.7 3.0 3.3 supply voltage ds1672-33 v cc 2.97 3.3 3.63 v 1 logic 1 v ih 0.7 x v cc v cc + 0.5 v 1 logic 0 v il -0.5 +0.3 x v cc v 1 backup supply voltage v backup 1.3 3.0 3.63 v 1 dc electrical characteristics ( v ccmin < v cc < v ccmax , t a = -40 ? c to +85 ?c.) parameter symbol min typ max units notes active supply current i cca 600 ? a 2 standby current i ccs 500 ? a 3 2.70 2.88 2.97 2.45 2.6 2.7 power-fail voltage v pf 1.58 1.7 1.8 v v backup leakage current i backuplkg 25 50 na logic 0 output (v ol = 0.4v) i ol 3 ma 1, 4 (v cc > 2v; v ol = 0.4v) 3 logic 0 output (ds1672-2) (v cc < 2v; v ol = 0.2 x v cc ) i ol 3 ma 1, 4 note 1: all voltages referenced to ground. note 2: i cca specified with scl clocking at max freque ncy (400khz), trickle charger disabled. note 3: i ccs specified with v cc = v cctyp and sda, scl = v cctyp , trickle charger disabled. note 4: sda and rst .
ds1672 4 of 15 dc electrical characteristics ( v cc = 0v , t a = -40 ?c to +85 ?c.) parameter symbol min typ max units notes v backup current (oscillator on) i backuposc 0.425 1 ? a 5 v backup current (oscillator off) i backup 200 na note 5: using the recommended crystal on x1 and x2. crystal specifications * parameter symbol min typ max units notes nominal frequency f o 32.768 khz series resistance esr 45 k ? load capacitance c l 6 pf *the crystal, traces, and crystal input pins should be isolat ed from rf generating signals. refer to application note 58: cryst al considerations for dallas real-time clocks for additional specifications
ds1672 5 of 15 ac electrical characteristics (v cc = 0v, t a = -40 ?c to +85 ?c.) parameter symbol conditions min typ max units notes fast mode 100 400 scl clock frequency f scl standard mode 100 khz fast mode 1.3 bus free time between a stop and start condition t buf standard mode 4.7 ? s fast mode 0.6 hold time (repeated) start condition t hd:sta standard mode 4.0 ? s 6 fast mode 1.3 low period of scl clock t low standard mode 4.7 ? s fast mode 0.6 high period of scl clock t high standard mode 4.0 ? s fast mode 0.6 setup time for a repeated start condition t su:sta standard mode 4.7 ? s fast mode 0 0.9 data hold time t hd:dat standard mode 0 ? s 7, 8 fast mode 100 data setup time t su:dat standard mode 250 ns 9 fast mode 20 + 0.1c b 300 rise time of both sda and scl signals t r standard mode 1000 ns 10 fast mode 20 + 0.1c b 300 fall time of both sda and scl signals t f standard mode 300 ns 10 fast mode 0.6 setup time for stop condition t su:sto standard mode 4.0 ? s capacitive load for each bus line c b 400 pf 10 i/o capacitance c i/o 10 pf note 6: after this period, the first clock pulse is generated. note 7: a device must internally provide a hold time of at least 300ns for the sda signal (referenced to the v ihmin of the scl signal) in order to bridge the undefined region of the falling edge of scl. note 8: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 9: a fast-mode device can be used in a st andard-mode system, but the requirement t su:dat to 250ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the lo w period of the scl signal, it must output the next data bit to the sda line t r max + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 10: c b ?total capacitance of one bus line in pf.
ds1672 6 of 15 power-up/power-dow n characteristics (t a = -40 ?c to +85 ?c) parameter symbol min typ max units notes v cc detect to rst (v cc falling) t rpd 10 s v cc detect to rst (v cc rising) t rpu 250 ms 11 v cc fall time; v pf(max) to v pf(min) t f 300 ? s v cc rise time; v pf(min) to v pf(max) t r 0 ? s note 11: if the eosc bit in the control register is set to logic 1, t rpu is equal to 250ms plus the startup time of the crystal oscillator. warning: negative undershoots below ?0.3v while the part is in battery-backed mode can cause loss of data. figure 1. timing diagram scl start sda stop t buf repeated start t hd:sta t low t hd:sta t hd:dat t su:dat t high t su:sta t f t su:sto figure 2. power-up/power-down timing outputs v cc v pf(max) inputs high impedance r st don't care valid recognized recognized valid t rpd v pf(min) t f t pd t r t rpu
ds1672 7 of 15 pin description pin name function 1, 2 x1, x2 connections for standard 32.768khz quartz crystal. the inte rnal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (cl) of 6pf. fo r more information about crystal selection and crystal layout considerations, refer to application note 58: crystal considerations with dallas real-time clocks. the ds1672 can also be driven by an external 32.768khz osci llator. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated . 3 v backup battery input for any standard 3v lithium cell or other energy source. battery voltage must be held betw een 1.3v and 3.63v for proper operation. diodes placed in series between the power source and the v backup may result in improper operation. if a backup supply is not required, v backup must be grounded. ul recognized to ensure agains t reverse charging current when used in conjunction with a lithium battery (c harger disabled). see ?conditions of acceptability? at www.maxim-ic.com/qa/info/ul . 4 gnd ground. dc power is provide d to the device on this pin. 5 sda serial-data input/output. sda is the input/output pin for the i 2 c serial interface. the sda pin is open drain and requires an external pullup resistor. 6 scl i 2 c serial-clock input. scl is used to synchronize data movement on the serial interface and requires an external pullup resistor. 7 rst active-low reset output. it functions as a microprocessor reset signal. this pin is an open-drain output and requires an external pullup resistor. 8 v cc power pin for primary power supply. when v cc is applied within normal limits, the device is fully accessible and data can be written and read. when v cc is below v pf , reads and writes are inhibited. figure 3. recommended layout for crystal local ground plane (layer 2) x1 crystal x2 gnd
ds1672 8 of 15 detailed description the ds1672 provides a 32-bit counter that increments once-per-second. the counter data is accessible via an i 2 c serial interface. a precision, temperature-compensated, voltage reference and comparator circuit monitors v cc . when v cc drops below v pf , rst becomes active and the in terface is disabled to prevent data corruption. the device switches to the backup supply input , which maintains oscillator and counter operation while v cc is absent. when v cc rises above v pf , rst remains low for a period of time (t rpu ) to allow v cc to stabilize. the block diagram in figure 4 shows the main el ements of the ds1672. as shown, communications to and from the ds1672 occu r serially over a i 2 c, bidirectional bus. the ds1672 operates as a slave device on the i 2 c bus. access is obtained by implementing a start condition and pr oviding a device identification code followed by a register address. s ubsequent registers can be accessed sequentially until a stop condition is executed. figure 4. block diagram oscillator circuit the ds1672 uses an external 32.768khz crystal. the oscillator circuit does not require any external resistors or capacitors to operate. table 1 specifies several crystal parameters for the ex ternal crystal. figure 4 shows a functional schematic of the oscillator circuit. if using a crystal with the specified charac teristics, the startup time is usually less than one second. table 1. crystal specifications* parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 45 k ? load capacitance c l 6 pf * the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations with dallas real-time clocks. 32-bit counter (4 bytes) i 2 c interface x1 x2 power control address register control logic 1hz v cc v backup gnd scl sda control trickle charger r st c c l l oscillator and divider dallas n semiconductor ds1672
ds1672 9 of 15 clock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circui t and the capacitive load for which the crystal was trimmed. additional error will be added by crystal frequency drift caused by temperature shifts. external circuit noise coupled into the os cillator circuit may result in the clock running fast. refer to application note 58: ?crystal considerations with dallas real-time clocks? for detailed information. address map the counter is accessed by reading or writing the first 4 bytes of the ds1672 (00h?03h). the control register and trickle charger are acces sed by reading or writing the appropriate register bytes as illustrated in table 2. if the master continues to send or request more data after the address pointer has reached 05h, the address pointer will wr ap around to location 00h. table 2. registers address b7 b6 b5 b4 b3 b2 b1 b0 function 00h lsb counter byte 1 01h counter byte 2 02h counter byte 3 03h msb counter byte 4 04h eosc control 05h tcs tcs tcs tcs ds ds rs rs trickle charger power control the device is fully accessible and data can be written and ready only when v cc is greater than v pf . however, when v cc falls below v pf , (point at which write protection oc curs) the internal clock registers are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . oscillator and counter operation are maintained from the v backup source until v cc is returned to nominal levels (see table 3). table 3. power control supply condition read/write access rst powered by v cc < v pf , v cc < v backup no active v backup v cc < v pf , v cc > v backup no active v cc v cc > v pf , v cc < v backup yes inactive v cc v cc > v pf , v cc > v backup yes inactive v cc oscillator control the eosc bit (bit 7 of the control register) controls the oscillator when in back- up mode. this bit when set to logic 0 will start the oscillator. when this bit is set to a logic 1, the oscillator is stopped and the ds1672 is placed into a low-power standby mode (i backup ) when in backup mode. when the ds1672 is powered by v cc, the oscillator is always on regardless of the status of the eosc bit; however, the counter is incremented only when eosc is a logic 0.
ds1672 10 of 15 microprocessor monitor a temperature-compensated comparator circuit monitors the level of v cc . when v cc falls to the power- fail trip point, the rst signal (open drain) is pu lled active and read/write ac cess is inhibited. when v cc returns to nominal levels, the rst signal is kept in the active state for t rpu (typically) to allow the power supply and microprocessor to stabili ze. note, however, that if the eosc bit is set to a logic 1 (to disable the oscillator during write protection), the reset signal will be kept in an active state for t rpu plus the startup time of the oscillator. trickle charger the trickle charger is cont rolled by the trickle charge register . the simplified schematic of figure 5 shows the basic components of the trickle charger. th e trickle charge select (t cs) bit (bits 4?7) controls the selection of the tric kle charger. in order to prevent accidental enabling, only a pattern on 1010 will enable the trickle charger. all ot her patterns will disabl e the trickle charger. the ds1672 powers up with the trickle charger disabled. the di ode select (ds) bits (bits 2, 3) select whether or not a diode is connected between v cc and v backup . if ds is 01, no diode is selected or if ds is 10, a diode is selected. the rs bits (bits 0, 1) select whethe r a resistor is connected between v cc and v backup and what the value of the resistor is. the resistor selected by the resistor sele ct (rs) bits and the di ode selected by the diode select (ds) bits are as follows: tcs tcs tcs tcs ds ds rs rs function x x x x 0 0 x x disabled x x x x 1 1 x x disabled x x x x x x 0 0 disabled 1 0 1 0 0 1 0 1 no diode, 250 ? resistor 1 0 1 0 1 0 0 1 one diode, 250 ? resistor 1 0 1 0 0 1 1 0 no diode, 2k ? resistor 1 0 1 0 1 0 1 0 one diode, 2k ? resistor 1 0 1 0 0 1 1 1 no diode, 4k ? resistor 1 0 1 0 1 0 1 1 one diode, 4k ? resistor 0 0 0 0 0 0 0 0 initial default value?disabled diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. the maximum charging cu rrent can be calculated as illustrated in the following example. assume that a system power supply of 3v is applied to v cc and a super cap is connected to v backup . also assume that the trickl e charger has been enabled w ith a diode and resistor r2 between v cc and v backup . the maximum current i max would, therefore, be calculated as follows: i max = (5.0v - diode drop) / r1 ? (5.0v - 0.7v) / 2k ???? 2.2ma as the super cap changes, the voltage drop between v cc and v backup will decrease and, therefore, the charge current will decrease.
ds1672 11 of 15 figure 5. programmable trickle charger r1 v cc 250? v backup r2 1 of 16 select note: only 1010 enables 1 of 2 select 1 of 3 select tcs tcs tcs tcs ds ds rs rs 2k ? r3 4k ? tcs = trickle charger select ds = diode select bit 7 bit 6 bit 5 bit 4 bit 3 rs = r esistor select bit 2 bit 1 bit 0 trickle charge register
ds1672 12 of 15 i 2 c serial data bus the ds1672 supports a bidirectional i 2 c bus and data transmission prot ocol. a device that sends data onto the bus is defined as a transmitter and a device r eceiving data as a receiver. the device that controls the message is called a master. the de vices that are controlled by the ma ster are slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus acce ss, and generates the start and stop conditions. the ds1672 operates as a slave on the i 2 c bus. connections to the bus are made via the open-drain i/o lines sda and scl. within the bus specifications, a standard mode (100khz maximum clock rate) and a fast mode (400khz maximum cloc k rate) are defined. the ds1672 operates in both modes. the following bus protocol has been defined (figure 6): ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the da ta line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low, while the clock line is high, defines a start condition. stop data transfer: a change in the state of the data line from low to high, while the clock line is high, defines a stop condition. data valid: the state of the data line represents va lid data when, after a start condition, the data line is stable for the durati on of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a star t condition and terminated with a stop condition. the number of data bytes transferred between th e start and the stop c onditions is not limited, and is determined by the master device. the in formation is transferred byte-wise and each receiver acknowledges with a ninth bit. within the i 2 c bus specifications a standard mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master devi ce must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during th e acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition.
ds1672 13 of 15 figures 7 and 8 detail how data transfer is accomplished on the i 2 c bus. depending upon the state of the r/ w bit, two types of data transfer are possible: 1) data transfer from a master tran smitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a numbe r of data bytes. the slav e returns an acknowledge bit after each received byte. 2) data transfer from a slave tran smitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the ma ster returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next se rial transfer, the bus will not be released. the ds1672 can operate in the following two modes: 1) slave receiver mode (ds1672 write mode): serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is tran smitted. start and stop conditions are recognized as the beginning and e nd of a serial transfer. addre ss recognition is performed by hardware after reception of the slav e address and direction bit (figure 7). the slave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7-bit ds1672 address, which is 1101000, followed by the direction bit (r/ w ), which for a write is a 0. after receiving and decoding the slave address byte the ds1672 outputs an acknowledge on the sda line. afte r the ds1672 acknowledges the slav e address + write bit, the master transmits a word address to the ds1672. this will set the register pointer on the ds1672, with the ds1672 acknowledging the transfer. the master ma y then transmit zero or more bytes of data, with the ds1672 acknowledging each byte received. th e register pointer will increment after each byte is transferred. the master will generate a stop condition to terminate the data write. 2) slave transmitter mode (ds1672 read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by th e ds1672 while the serial clock is input on scl. start and stop conditions are rec ognized as the beginning and end of a serial transfer (figure 8). the slave address byte is the first byte received af ter the start condition is generated by the master. the slave address byte contains the 7-bit ds1672 address, which is 1101000, followed by the direction bit (r/ w ), which for a read is a 1. after receiving and decoding the slave address byte the ds1672 outputs an acknowledge on the sda line. the ds1672 then begins to tr ansmit data starting with the register address pointed to by the register pointer. if the re gister pointer is not written to before the initiation of a read mode the first address th at is read is the last one stored in the register pointer. the ds1672 must receive a ?not acknowledge? to end a read.
ds1672 14 of 15 figure 6. data transfer on i 2 c serial bus msb slave address r/w direction bit sda scl start condition 12 6789 12 89 stop condition or repeated start condition 3 - 8 acknowledgement signal from receiver acknowledgement signal from receiver ack ack repeated if more bytes are transferred figure 7. data write: slave receiver mode a xxxxxxxx a 1101000 s 0 xxxxxxxx a xxxxxxxx a xxxxxxxx a p s - start a - acknowledge p - stop r/w - read/write or direction bit address = d0h data transferred (x+1 bytes + acknowledge) figure 8. data read: slave transmitter mode a xxxxxxxx a 1101000 s 1 xxxxxxxx a xxxxxxxx a xxxxxxxx a p s - start a - acknowledge p - stop a - not acknowledge r/w - read/write or direction bit address = d1h data transferred (x+1 bytes + acknowledge); note: last data byte is followed by a not acknowledge (a) signal)
ds1672 15 of 15 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. thermal information package theta-ja theta-jc 8 dip (300 mils) 110c/w 40c/w 8 so (150 mils) 170c/w 40c/w 8 ? sop (3mm) 221c/w 39c/w package information for the latest package outline information and land patterns, go to www.maxim-ic.com/package s . package type package code document no. 8 pdip (300 mils) p8+1 21-0043 8 so (150 mils) s8+5 21-0041 8 ? sop u8+1 21-0036

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